HW/SW Co-design for Reliable TCAM-based In-memory Brain-inspired Hyperdimensional Computing
نویسندگان
چکیده
Brain-inspired hyperdimensional computing (HDC) is continuously gaining remarkable attention. It a promising alternative to traditional machine-learning approaches due its ability learn from little data, lightweight implementation, and resiliency against errors. However, HDC overwhelmingly data-centric similar algorithms. In-memory rapidly emerging overcome the von Neumann bottleneck by eliminating data movements between compute storage units. In this work, we investigate model impact of imprecise in-memory hardware on inference accuracy HDC. Our modeling based 14nm FinFET technology fully calibrated with Intel measurement data. We accurately model, for first time, voltage-dependent error probability in SRAM-based FeFET-based computing. Thanks HDC's errors, complexity underlying can be reduced, providing large energy savings up 6x. Experimental results SRAM reveal that variability-induced errors have 39 percent. Despite such high probability, only marginally impacted. This opens doors explore new tradeoffs. also demonstrate application-dependent. addition, robustness when realized using non-volatile FeFET devices instead mature CMOS-based SRAMs. does remain despite larger while area power obtained. All all, HW/SW co-design key efficient yet reliable both conventional CMOS upcoming technologies.
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ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 2023
ISSN: ['1557-9956', '2326-3814', '0018-9340']
DOI: https://doi.org/10.1109/tc.2023.3248286